In semiconductor memories, especially for erasable programmable read only memory (EPROM) and flash memory, some program/erase schemes thereof require negative supply voltages in addition to positive supply voltages. Typically, such negative voltages are supplied by use of charge-pumping circuits. However, the charge-pumping circuit occupies large chip area. To economize the area of silicon wafer, it is desired for circuit designers to have negative voltages supplied directly from appropriate pins during programming/erasing.
On the other hand, N-type device formed in P-type substrate or well connected between input pad and ground pad is usually served as ESD protection apparatus with the P-type substrate or well grounded under normal operation. FIG. 1 shows an ESD protection apparatus 10 for example implemented with NMOS, in which P+ region 14 and N+ regions 16 and 18 are formed on P-type substrate or well 12 with a gate 20 for ESD protection apparatus above the channel between the N+ regions 16 and 18, the N+ region 16 connected to input pad 22, and the N+ region 18 and P+ region 14 connected to ground pad 24. In the structure 10, however, a parasitic diode 26 is formed with the N+ region 16 and P-type substrate or well 12 between the input pad 22 and ground pad 24 and subsequently limits the applied negative voltage lower than −0.7V due to the forward-biased parasitic diode 26. Unfortunately, the negative supply voltage may be high up to −7V depending on the programming/erasing for various applications. It is therefore desired an ESD protection apparatus for dual-polarity supply voltages.